1. Technical Field
The present invention relates to communication systems, and in particular, to multi-lane serializer/deserializer (SERDES) clock and data skew alignment for multi-standard support in communication circuits.
2. Background Art
Communication systems for transmitting data may operate according to a number of standards and implementations. One such implementation is a SERDES communication channel that takes a given number of data bits from a digital domain, serializes the data, and transmits the data to a receiver that deserializes it for another digital domain. SERDES data transmission implementations can be used in a wide range of communication systems and devices, such as mobile devices, desktop computers and servers, computer networks, and telecommunication networks.
Communication systems may include multiple channels or lanes (e.g., multilane transceivers, etc.) for transmitting data, and this introduces difficulties in aligning data and clock signals across the multiple channels. For example, clock circuitry for different channels may start up in different states and cause a skew of the data from lane to lane. This skew should be removed for synchronous operation, as the skew from lane to lane can be as large as the lowest clock period. For high speed SERDES implementations, the output data rate relative to the low speed clock may cause the multi-channel skew to increase further. Previous solutions have relied on complex reset circuits to bring multiple channels up in the same state. However, reliability coming out of reset depends on careful, complex distribution of reset signals and relative timing to running clocks. Another complication exists in the difficulties of resetting high-speed clock dividers (referred to herein as “dividers”) as stringent timing margins and resettable high speed dividers require significant power and circuit area consumption. Additionally, asynchronous reset architectures have unacceptably high probabilities of failure.
Another concern for communication systems using SERDES with multiple channels is that multiplexors (MUX) used in the SERDES circuitry may have different architectures and timing characteristics. For example, two different MUX architectures may have different timing delays in propagating data. This leads to variations in timing across the channels and further exaggerates clock and data skew in the system even when data is transmitted from the digital domain at the same time.
The implementation of different communication standards in a system also complicates alignment in multichannel designs. Design dependency between multiple design cores and/or architectures also raises clock and data alignment difficulties. The previous solutions noted above cannot easily be added or modified, and this problem is further exacerbated by the inclusion of additional architectures and standards.